FIG. 1 shows a conventional digital temperature sensor (DTS) using a well-known type bandgap circuit 104 coupled to a conventional ratio meter circuit 101. The ratio circuit 101 includes a current-sources based DAC (digital-to-analog converter) 106 to generate a temperature dependant function M (a multiplier for the DAC) based on the zeroing of a Vout value from comparator 108. The bandgap circuit 102 may comprise a standard diode-based PTAT (proportional to absolute temperature) block, which produces two temperature dependent DC voltages, Vbe and ΔVbe. In some embodiments, the Vbe voltage has a negative temperature slope, while the ΔVbe voltage has a positive or flat temperature slope. Through the DAC 106, the ΔVbe voltage is multiplied by a factor M. The DAC 106 may comprise a conventional current source type DAC, such as that shown in FIG. 2. In this example, M is a discrete 4-bit value corresponding to an analog level that multiplies ΔVbe, resulting in a value of: MΔVbe (also referred to as a Vref voltage). The Vref voltage has positive or flat temperature dependence, its slope and offset being determined by M. FIG. 3 is a graph showing different exemplary curves for Vbe and Vref at different values of M and how they are dependent on temperature.
The comparator 108 is used to detect the value of M for which the negative-sloped Vbe voltage is crossed by the positive or flat -sloped Vref voltage, i.e., when: Vbe−Vref=0. The value of M corresponds to a particular temperature, which can be identified using any suitable manner, e.g., via a look-up table. It can be seen that circuit 101 acts as a ratio meter because M is a ratio between Vbe and ΔVbe, which corresponds to the temperature of the bandgap circuit 102.
Unfortunately, a disadvantage of this approach arise from the current-source type DAC. Only a few transistors are used for the least significant (LS) bit, but each successive bit has double the number of transistors. (Each bit path in FIG. 2 is shown to have a single reference transistor PiA, but each transistor may actually comprise one or more transistors, depending on how the circuit is implemented, to achieve an appropriate binary weighted DAC.) A problem rises when it is necessary to cover a significant dynamic range, which typically follows from normal process variations. for example, depending on design concerns, a 9-bit or even a 10-bit DAC range may be needed. (Even more, many more, bits would be needed when non-binary weighted embodiments are employed.) In these cases, the number of transistors becomes prohibitively high and they may be spread over a large area, which can create side effect problems such as excessive leakage, VT. variations, Ro. and drain effect variations, and the like. These effects can contribute to measurement errors, e.g., caused by differences in DAC behavior between the calibration and the system operation. In addition, when switching between different groups of current sources, the variations can cause the current to be a non-monotonic function of the digital bits. This can result in significant temperature errors. Another problem may be poor PSRR (power supply rejection ratio) of the DAC, which typically requires a good SFR (super filtered regulator) to supply power for the DTS. Adding the SFR leads to increased area, power consumption and an added need for calibration.
Accordingly, a new approach is desired.